SUBLEQ CPU
An open-source, single-instruction processor core for education, experimentation, and FPGA deployment.
Overview
SUBLEQ (Subtract and Branch if Less than or Equal to zero) is a minimalist computer architecture built around a single instruction. Despite its simplicity, a SUBLEQ machine is Turing-complete — any program can be expressed as a sequence of memory operations.
The OpenSiliconHub SUBLEQ CPU project aims to provide a clean, well-documented RTL implementation suitable for FPGA synthesis, simulation, and teaching how processors work from the ground up.
Instruction Format
Each instruction is three memory addresses:
SUBLEQ A, B, C — subtract the value at address B from the value at address A, store the result at A, then branch to C if the result is ≤ 0.
Special addresses are reserved for I/O and halting, keeping the datapath compact while still supporting interactive programs.
Goals
- Provide a readable, synthesizable Verilog/VHDL core
- Support FPGA targets with a simple memory-mapped I/O model
- Include example programs and an assembler toolchain
- Serve as a reference design for custom SoC and educational use
Status
This project is in early development. Core architecture is defined and initial RTL is being drafted. Contributions, review, and test program ideas are welcome.